It computes
A full 8-bit ALU sits behind thirty-two opcodes. Arithmetic, logic, shifts, memory, branches, input and output all run through the same gate table.
32 OPCODES · 8-BIT DATA PATH
ONE PRIMITIVE · ONE EDGE PER TRANSACTION · SOLANA
A CPU that clocks with the chain.
Runnet CPU is a gate-level 8-bit processor built from NAND gates and walked one clock edge at a time. The browser runs the same netlist the Solana program executes, so the machine on this page is computation, not a video of computation.
NAND gates2,161
Flip-flops167
Clock1 TX
Ticker$RUNCPU
00 / WHAT
Four properties you can check yourself.
The machine is small enough to inspect and complete enough to behave like a real processor. Its gate table, assembler, browser machine and chain logic all follow the same RN-8 design.
It remembers
Sixteen registers and 256 bytes of RAM are latched with the machine. State survives from one edge to the next instead of being reconstructed by the interface.
16 × 8-BIT REGISTERS · 256 B RAM
It accepts input
Each step carries an input value. Programs can read it through the input port and place a result on the output port for another contract or application to use.
1 BYTE IN · 1 BYTE OUT
It is replayable
The ROM and every sponsored input are enough to replay the machine from reset. A deterministic processor makes every historical edge independently checkable.
DETERMINISTIC · RE-EXECUTABLE
01 / MACHINE
Nothing here is pre-rendered.
Press step and the browser evaluates all 2,161 NAND gates in topological order, then latches every flip-flop together. The white pixels in the die view are gates that changed on the current edge.
10 CYC/S
42
02 / BUILD
From one NAND gate to a contract.
The processor description places logic one primitive at a time. The optimiser removes dead and duplicate work, verification runs against the resulting netlist, and that same table feeds both the browser and the contract toolchain.
01
NAND
One primitive. Adders, muxes, decoders and storage are composed from it.
02
PLACE
The builder lays out the processor in call order, which is already dependency order.
03
PRUNE
Constants fold, repeated logic is shared, and logic with no reader disappears.
04
PROVE
Exhaustive arithmetic and differential machine checks must pass before output is written.
05
SOLANA
The native program executes the same gate table and stores the public machine state in a Solana account.
03 / ISA
Five bits. Thirty-two opcodes.
The opcode field is completely occupied. The row matching the instruction currently executing in the machine above lights white.
| OP | MNEMONIC | FORM | EFFECT |
|---|
04 / CLOCK
Anyone can take the next edge.
Runnet CPU lives on Solana. Each public step transaction advances exactly one RN-8 clock edge when the live machine is online.
Solana
CLUSTER
MAINNET-BETA
NETWORK
SOLANA
NATIVE
SOL
CPU
COMING SOON
COIN
$RUNCPU
No wallet connected.
On-chain readout
Read the current public machine state directly from Solana when the live processor is online.
Cycle—
PC—
Out—
Flags—
05 / BUILD ONE
Write a program. Burn it into a chip.
Write RN-8 assembly, run it across the real 2,161-gate netlist, and create a working RN-8 machine account on Solana.
Runnet CPU
The reference chip carries the Runnet identity and the $RUNCPU ticker. New programs can be assembled and simulated from the workbench.
$RUNCPU
Launch path
1. Write or paste RN-8 assembly.
2. Assemble against the shipped opcode table.
3. Run it on all 2,161 NAND gates in your browser.
4. Create and seal the RN-8 machine account on Solana.
5. Advance the live machine with public Solana step transactions.
06 / INSTRUMENT
The browser is the instrument.
The browser executes the full processor locally, while Solana carries the public machine state. Every edge can be inspected from gates to registers.
GATES / EDGE2,161
Every clock edge evaluates the full topological gate table.
VERIFICATION1,052,672
Exhaustive combinational vectors in the silicon build before the netlist is emitted.
BROWSER CORE0
The processor runs directly in the browser with no remote emulator service.
07 / ROADMAP
One processor family. Wider generations beside it.
New silicon can be added beside the deployed RN-8 program rather than replacing it. Each generation can keep its own account layout and verified gate table.
R0
RUNNET CPU
8-bit gate-level processor, browser machine, assembler and Solana clock.
R1
LAUNCHPAD
Program workbench, chip design data, factory deployment and per-chip token integration.
R2
WIDER SILICON
16-bit and later generations produced from the same primitive and validated through the same interface.
R3
VERIFICATION COURT
Off-chain execution with a disputed edge recomputed by the deployed gate array.